The present invention relates to integrated circuits generally, and particularly to integrated circuits which are closely associated with a microprocessor.
Microprocessors will commonly have two types of externally initiated branching conditions, namely Resets and Interrupts. (The term "interrupt" is often used more generically, but in this application the term interrupt will be used to exclude Reset signals.) Typically an Interrupt signal will cause the microprocessor to halt execution of its current program, and branch to an interrupt-handling routine. (The interrupt-handling routine may be, for example, a routine which polls possible interrupt sources, to find where the interrupt actually came from.) By contrast, a Reset signal will not only cause the microprocessor to halt execution of its current program, but will also cause the microprocessor to set all of its logic to a predetermined state. Thus, a Reset is a more drastic action than an interrupt.
Resets are extremely useful insurance, since they do provide a way to retrieve a microprocessor from a "stuck" state. It can often happen that a software error will cause a microprocessor to remain in a state where it is looping, or waiting for an impossible event to happen; and in many such cases nothing short of a Reset may be able to return the microprocessor to normal operation.
Interrupts are particularly useful for real-time control applications. In such applications, interrupts generated by real-time circumstances provide a way for the microprocessor's program flow to be synchronized with external events (of some known type).
Microprocessors must often keep track of two clocks: one clock for time of day, and one clock which is used as an interval timer. In many systems, one or both of these clocks is maintained by circuits external to the microprocessor. If the interval timer is external to the microprocessor, an Interrupt signal will often be used to signal the end of an interval which the microprocessor has previously programmed into the interval timer.
Since software faults can cause microprocessors to lock up, and since it is very difficult to eliminate all possible software faults, it has been suggested that a "watchdog" chip could be used to minimize the problem of lockup. The "watchdog" chip would be a simple integrated circuit, which would send a Reset command to the microprocessor whenever the microprocessor appeared to be locked up. A possible lockup condition can be detected, for example, by having the watchdog chip monitor the microprocessor's output lines, and initiate an interrupt, and then a Reset, if no activity is seen for a very long time interval. Alternatively, the watchdog chip may include an interval timer, and be programmed to send a Reset command if its interval timer ever counts down to zero. In this case, the microprocessor (in addition to its primary program flow) would periodically reprogram the watchdog's interval timer, so that the watchdog's interval timer never counts down to zero while the microprocessor is fully operational. Since the watchdog function is relatively simple, other functions may be combined with it.
The extra insurance provided by the watchdog operation does impose some burden on the software structure. Therefore, it is highly desirable, in many applications, for end users to have the capability to disable the watchdog operation.
In low-power applications, it is often desirable for the processor to go to sleep until a specified time, regardless of intervening events. (This is often an objective in systems using microprocessors such as the 80C51, 80C31, 68HC05, 68HC11, or 146805 models) Thus, the processor in such a case may wish to receive an interrupt signal from the timer, but not receive any Reset signals which may be generated in the interim.
Thus, these considerations imply some conflict regarding possible uses of the interrupt and Reset pins.
The present invention provides an innovative improvement in microprocessor support chips, which is also applicable to a wide range of integrated circuits generally.
The present invention provides an integrated circuit which includes, as part of its I/O interface for certain pins, logic for steering the signals. Thus, the Reset and Interrupt pins, in the example of the presently preferred embodiment, can be swapped at will, by rewriting the data values in a (battery-backed nonvolatile) memory cell whose output controls the logic to switch the data routing from one of two or more internal logic lines to the pins (and associated drivers, ESD protection circuits, etc.).
This functionality goes beyond a mere reconnection of wires. In the presently preferred embodiment, the I/O buffers used are programmable in other features as well. For example, in the presently preferred embodiment, the output buffers can be set to either sink or source current when an interrupt occurs, and they can be set to provide a pulsed output or a constant output.
It should also be noted that, although the presently preferred embodiment uses pinmapping logic to select and modify the output buffer used for outgoing interrupts, this concept can also be adapted to provide selection among alternative input buffers. This too may be very advantageous in some applications, as will be discussed below.
The presently preferred embodiment permits two pins, on which outgoing interrupts are routed, to be exchanged as desired. It should be noted that, among the options provided by this embodiment, the interrupts driven onto these pins can be defined either as pulses or as constant levels. Thus, the integrated circuit of this embodiment can be used to provide interrupts to either a level-sensitive or an edge-sensitive input of another integrated circuit. This is particularly convenient where compatibility with existing system practices, or with other integrated circuit designs, may mean that certain signals may be defined according to one or the other of these two standards. For example, in many microprocessor architectures, the Reset and Interrupt pins are defined differently: Reset signals are very commonly defined as level-related signals, and interrupts are very commonly defined as edge-related.
Thus, the present invention is particularly advantageous in integrated circuits which implement a functionality which is ancillary to a microprocessor. A wide variety of such architectures have been proposed, and the "watchdog" operation of the preferred embodiment is merely one example. In applications of this kind, the ability to remap the outgoing stream of interrupts is particularly advantageous, since it increases the versatility of the ancillary chip. Such versatile chips, which can coordinate with more than one microprocessor, can greatly increase a system designer's options, and may also increase the speed with which a system design can be completed.
However, it should also be noted that the novel concepts in this embodiment can be further adapted to a much wider range of embodiments. In general, the present invention permits the interface characteristics of a pin to be separated from the signals which are sent or received over that pin.
Thus, for example, various pins of a single packaged device may or may not have the ability to go into a high-impedance state (be tristated); may interface to various signal families (e.g. single-ended ECL, differential ECL, TTL, or full CMOS levels); may have higher or lower source impedance (depending on the size of the driver transistors used at an output); and higher or lower input impedance (depending on the device types used for the first-stage input buffer and ESD protection).
The present invention permits the pins to be remapped onto signals. This capability can be particularly advantageous in biCMOS integrated circuits: a growing number of integrated circuits use this hybrid technology, where designers can use PMOS, NMOS, or NPN transistors. This capability is being adapted for a variety of purpose: one direction of development is to introduce a limited number of bipolar drivers into a mostly-CMOS circuit design, at points where a strong drive capability is needed (typically at external pins, or sometimes for driving long internal busses). Another line of development is to use bipolar logic for the key internal data paths of a chip which still has normal CMOS interface standards. Another line of development is used in analog design, where the high gains available from bipolar devices can be used to advantage in a largely-CMOS circuit design. A related field is for high-voltage devices, where specialized bipolar devices may be used to switch high voltages. In many of these subclasses of biCMOS, the use of CMOS is motivated by the very low static power consumption of CMOS logic and memory. Another powerful motivating factor is compatibility with the very large installed base of system designs which are primarily built around CMOS integrated circuits.
The present invention can be particularly advantageous in such contexts. The present invention enables integrated circuits wherein (for example) the output driver size can be optimized for the particular application contemplated, to minimize power consumption. Similarly, integrated circuits which have ECL internal logic can provide the option of bringing out ECL levels at a pin, so that systems which are able to use this capability can avoid the additional delay caused by translation to CMOS I/O levels. This flexibility can also provide system designers the option of combining small sections of ECL local busses with a largely-CMOS architecture.
The innovative pin-remapping structures can also be particularly useful in applications using analog and hybrid technologies. This capability can be used to permit users to dynamically change the I/O buffers in accordance with the signal types expected for various signals.
However, the range of potential applications is even larger than this. Such pin-remapping structures can be used to address a tremendous variety of applications, in digital, analog, and hybrid technologies. This provides a generally applicable tool for adaptable integrated circuits, including, but not limited to, "glue" logic circuits, application-specific integrated circuits (ASICs), and semi-custom integrated circuits. In fact, the flexibility provided by the present invention may permit standard integrated circuit designs to be used in many locations where ASICs or semicustom ICs might otherwise have to be used.